1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and relates, for example, to a shape of a semiconductor chip having excellent deflecting strength and a manufacturing method thereof.
2. Related Background Art
A manufacturing process of a semiconductor device includes a dicing step to cut a semiconductor wafer by use of a blade or the like so as to divide the semiconductor wafer into pieces after element formation.
One example of the conventional dicing step will be described as a first conventional example referring to FIGS. 30 to 37. It should be noted that the same reference numerals are given to the same parts in the following drawings, and therefore repeated explanation of those parts will be described only when necessary.
First, as shown in FIG. 30, a protection tape PT is affixed to an element formation surface (hereinafter referred to as a main surface) 100MS of a semiconductor wafer W, and then a rear surface of the semiconductor wafer W is polished by mechanical grinding or etching using a grindstone 210 or the like to finish with a predetermined thickness, as shown in FIG. 31. It should be noted that in the present application, the term “etching” is used to express not only chemical processing, but also chemical mechanical polishing (CMP).
Next, a dicing tape DT is affixed to the rear surface of the semiconductor wafer W and attached to a wafer ring WR, and then a product to be processed is flipped over (transferred) to peel off the protection tape PT on the main surface 100MS, as shown in FIG. 32. Subsequently, as shown in FIG. 33, the semiconductor wafer W is cut by use of a blade BD or the like from its main surface 100MS along dicing lines provided on the main surface 100MS in accordance with the size of semiconductor chips, thereby dividing the semiconductor wafer W into pieces as shown in FIG. 34. The dicing tape DT affixed to the rear surface of the semiconductor wafer W prevents the semiconductor chips from being scattered after wafer division.
In the dicing method described above, chipping attributed to mechanical cutting has frequently occurred at edge portions where the rear surface and side surfaces of the semiconductor chip cross due to cutting for wafer division. For example, as shown in a perspective view of FIG. 35, a number of chippings CP are caused at the edge portions where side surfaces 100SA to 100SD and a rear surface 100RS of a semiconductor chip 100 cross, and their sizes range from about 1 μm to about 60 μm, with an average of about 20 μm.
FIG. 36 is a photograph of the semiconductor chip 100 taken from its rear surface side in a direction of an arrow AR90 of FIG. 34 before the semiconductor chip 100 is removed from the dicing tape DT. FIG. 37 is a photograph of an intersection of the side surface 100SA and the rear surface 100RS taken in a direction of an arrow AR100 of FIG. 35. FIG. 37 clearly shows occurrence of a chipping 100CP.
Such a chipping significantly affects deflecting strength (bending strength) of a semiconductor element, causes defects in, for example, an assembly process for packaging the semiconductor element, and decreases a final product yield ratio.
In order to prevent the chipping described above, a technique has been proposed in which a groove is formed along the dicing lines in advance to prevent the chipping, and thereafter the semiconductor wafer is cut along the groove to hold the chipping inside the groove so as to reduce an influence to the wafer surface (e.g., Japanese Patent Publication Laid-open No. 2003-100666).
However, the dicing step according to a second conventional example disclosed in Japanese Patent Publication Laid-open No. 2003-100666 is not a technique to eliminate the chipping itself. Indeed, it can reduce the influence to the wafer surface, but leaves a problem that a chipping 150CP still occurs, for example, as shown in photographs of FIG. 38 and FIG. 39.